CD74HC192PWR

高速CMOS逻辑可预置同步4位加/减计数器 High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.

Presetting the counter to the number on the preset data inputs P0-P3 is accomplished by a LOW asynchronous parallel load input PL\\\\. The counter is incremented on the low-to-high transition of the Clock-Up input and a high level on the Clock-Down input and decremented on the low to high transition of the Clock-Down input and a high level on the Clock-up input. A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up carry goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down borrow in the count down mode likewise goes low half a clock period before the maximum count 9 in the 192 and 15 in the 193 and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.

If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.