72兆位的DDR -II + SRAM 2字突发架构( 2.5周期读延迟) 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency
SRAM - 同步,DDR II 存储器 IC 72Mb(2M x 36) 并联 165-FBGA(15x17)
得捷:
IC SRAM 72MBIT PARALLEL 165FBGA
艾睿:
SRAM Chip Sync Single 1.8V 72M-Bit 4M x 18 0.45ns 165-Pin FBGA