时钟合成器/抖动清除器 Synchronizer & Adapt Clock Transla
Product Details
The 10 clock outputs of the AD9542 are synchronized to any one of up to four input references. The digital phase-locked loops DPLLs reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.
The AD9542 is available in a 48-lead LFCSP 7 mm × 7 mm package and operates over the −40°C to +85°C temperature range.
Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.
Applications
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- SyncE jitter cleanup and synchronization
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- Optical transport networks OTN, SDH, and macro and small cell base stations
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- OTN mapping/demapping with jitter cleaning
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- Small base station clocking, including baseband and radio
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- Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
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- JESD204B support for analog-to-digital converter ADC and digital-to-analog converter DAC clocking
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- Cable infrastructures
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- Carrier Ethernet
### Features and Benefits
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- Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references
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- Complies with ITU-T G.8262 and Telcordia GR-253
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- Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825
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- Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb
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- Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
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- Programmable digital loop filter bandwidth: 10−4 Hz to 1850 Hz
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- Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
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- Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
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- 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs 1 Hz to 500 MHz
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- 2 differential or 4 single-ended input references
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- Crosspoint mux interconnects reference inputs to PLLs
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- Supports embedded modulated input/output clock signals
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- Fast DPLL locking modes
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- Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
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- External EEPROM support for autonomous initialization
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- Single 1.8 V power supply operation with internal regulation
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- Built in temperature monitor/alarm and temperature compensation for enhanced zero delay performance
