CDCLVD1213RGTT

1 ： 4低附加抖动LVDS缓冲器，带有分频器 1:4 Low Additive Jitter LVDS Buffer With Divider

The is a Clock Buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL or CML. The CDCLVD1213 contains a high performance divider for one output QD which can divide the input clock signal by a factor of 1, 2 or 4. The CDCLVD1213 is specifically designed for driving 50R transmission lines. The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in 2.5V supply environment and is characterized from -40 to 85°C ambient temperature.

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1:4 Differential buffer

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Universal input accepts LVDS, LVPECL and CML

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4 LVDS outputs, ANSI EAI/ A-644A standard compatible

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20ps Maximum low output skew

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Green product and no Sb/Br