CDCVF855PW

2.5V 锁相环 DDR 时钟驱动器 28-TSSOP -40 to 85

The CDCVF855 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair CLK, CLK to 4 differential pairs of clock outputs Y[0:3], Y[0:3] and one differential pair of feedback clock outputs FBOUT, FBOUT. The clock outputs are controlled by the clock inputs CLK, CLK, the feedback clocks FBIN, FBIN, and the analog power input AVDD. When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state 3-state and the PLL is shut down low-power mode. The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz typical 10 MHz. An input frequency-detection circuit detects the low-frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs.

When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF855 is also able to track spread-spectrum clocking for reduced EMI.

Because the CDCVF855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCVF855 is characterized for both commercial and industrial temperature ranges.