2.5 -V锁相环时钟驱动器 2.5-V PHASE-LOCK LOOP CLOCK DRIVER
The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair CLK, CLK to 10 differential pairs of clock outputs Y[0:9], Y[0:9] and one differential pair of feedback clock outputs FBOUT, FBOUT. The clock outputs are controlled by the clock inputs CLK, CLK, the feedback clocks FBIN, FBIN, and the analog power input AVDD. When PWRDWN is high, theoutputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state 3-state and the PLL is shut down low-power mode. The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz typical 10 MHz. An input frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs.
When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857B is characterized for both commercial and industrial temperature ranges.
频率 200 MHz
电源电压DC 2.50 V
输出接口数 10
供电电流 12 mA
电路数 1
输出电流驱动 12.0 mA
输入数 1
最大占空比 60 %
下降时间Max 0.9 ns
上升时间Max 0.9 ns
工作温度Max 85 ℃
工作温度Min -40 ℃
电源电压 2.3V ~ 2.7V
电源电压Max 2.7 V
电源电压Min 2.3 V
安装方式 Surface Mount
引脚数 48
封装 TSSOP-48
长度 12.5 mm
宽度 6.1 mm
高度 1.15 mm
封装 TSSOP-48
工作温度 -40℃ ~ 85℃
产品生命周期 Active
包装方式 Tube
RoHS标准 RoHS Compliant
含铅标准 Lead Free
REACH SVHC版本 2015/06/15
ECCN代码 EAR99
型号/品牌 | 代替类型 | 替代型号对比 |
---|---|---|
CDCV857BIDGG TI 德州仪器 | 当前型号 | 当前型号 |
CDCV857BIDGGG4 德州仪器 | 完全替代 | CDCV857BIDGG和CDCV857BIDGGG4的区别 |
CDCV857ADGGR 德州仪器 | 类似代替 | CDCV857BIDGG和CDCV857ADGGR的区别 |
CDCV857BDGG 德州仪器 | 类似代替 | CDCV857BIDGG和CDCV857BDGG的区别 |