CDC2516DGGR

具有三态输出的 3.3V 相位锁定环时钟驱动器 48-TSSOP 0 to 70

The CDC2516 is a high-performance, low-skew, low-jitter, phase-lock loop PLL clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output FBOUT to the clock CLK input signal. It is specifically designed for use with synchronous DRAMs. The CDC2516 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground.

The CDC2516 is characterized for operation from 0°C to 70°C.