CDC341DW

1线路至8线路时钟驱动器 1-LINE TO 8-LINE CLOCK DRIVER

The CDC341 is a high-performance clock-driver circuit that distributes one A input signal to eight Y outputs with minimum skew for clock distribution. Through the use of the control pins 1G and 2G, the outputs can be placed in a low state regardless of the A input.

The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND.

The CDC341 is characterized for operation from 0°C to 70°C.

得捷:
IC CLK BUFFER 1:8 80MHZ 20SOIC

立创商城:
CDC341DW

德州仪器TI:
1-to-8 TTL clock driver with output control pins for low state

艾睿:
Clock Fanout Buffer 8-OUT 1-IN 1:8 20-Pin SOIC Tube

安富利:
Clock Fanout Buffer 8-OUT 20-Pin SOIC Tube

Chip1Stop:
Clock Fanout Buffer 8-OUT 20-Pin SOIC Tube

Verical:
Clock Fanout Buffer 8-OUT 1-IN 1:8 20-Pin SOIC Tube

Newark:
# TEXAS INSTRUMENTS  CDC341DW  CLOCK DRIVER, 80MHZ, SOIC-20

Win Source:
Clock Fanout Buffer Distribution IC 80MHz 20-SOIC 0.295", 7.50mm Width