CDCLVP215RHBT

低电压双通道差分1 ： 5 LVPECL时钟驱动器 LOW-VOLTAGE DUAL DIFFERENTIAL 1:5 LVPECL CLOCK DRIVER

The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, CLKA, CLKB to 5 pairs of differential LVPECL clock QA0..QA4, QB0..QB4 outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50- transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50 .

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLKA or CLKB and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP215 is characterized for operation from –40°C to 85°C.