CDCLVP2102RGTT

TEXAS INSTRUMENTS  CDCLVP2102RGTT  芯片, 时钟缓冲器, 双, 1:2, LVPECL, 16QFN

The is a highly versatile low additive Jitter Buffer can generate four copies of LVPECL clock outputs from two LVPECL, LVDS or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1ps, RMS from 10kHz to 20MHz and overall output skew is as low as 10ps, making the device a perfect choice for use in demanding applications. The CDCLVP2102 clock buffer distributes two clock inputs IN0, IN1 to four pairs of differential LVPECL clock outputs OUT0, OUT3 with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS or LVCMOS/LVTTL. The CDCLVP2102 is specifically designed for driving 50R transmission lines.

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1:2 Differential buffer

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Two clock inputs

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Universal inputs can accept LVPECL, LVDS, LVCMOS/LVTTL

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Four LVPECL outputs

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2GHz Maximum clock frequency

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48mA Maximum core current consumption

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<100fs Very low additive jitter

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10ps Maximum output skew

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Green product and no Sb/Br

Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.