CDC318ADLRG4

具有 I2C 控制接口的 1 线至 18 线路时钟驱动器 48-SSOP 0 to 70

Clock Fanout Buffer Distribution, Data IC 1:18 100MHz 48-BSSOP 0.295", 7.50mm Width

得捷:
IC CLK BUFFER 1:18 100MHZ 48SSOP

立创商城:
CDC318ADLRG4

艾睿:
Clock Fanout Buffer 18-OUT 1-IN 1:18 48-Pin SSOP T/R

安富利:
The CDC318 is a high-performance clock buffer that distributes one input A to 18 outputs Y with minimum skew for clock distribution. The CDC318 operates from a 3.3-V power supply, and is characterized for operation from 0°C to 70°C.The device provides a standard mode 100K-bits/s I2C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs SDATA and SCLOCK provide integrated pullup resistors typically 140 kΩ and are 5-V tolerant.Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register. The registers are write only and must be accessed in sequential order i.e., random access of the registers is not supported.The CDC318 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a high-impedance state via the output-enable OE input. When OE is high, all outputs are in the operational state. When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.

Chip1Stop:
Clock Fanout Buffer 18-OUT 48-Pin SSOP T/R

Verical:
Clock Fanout Buffer 18-OUT 1-IN 1:18 48-Pin SSOP T/R