CD74AC139M

TEXAS INSTRUMENTS  CD74AC139M  逻辑芯片, 译码器/信号分离器, 双路, 2-4线, 16SOIC

The is a 2-to-4 dual Decoder/Demultiplexer designed for 1.5 to 5.5V VCC operation. It is to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The active-low enable G\\ input can be used as a data line in demultiplexing applications. It features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

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Buffered inputs

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Incorporate two enable inputs to simplify cascading and/or data reception

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Speed of bipolar F, AS and S, with significantly reduced power consumption

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Balanced propagation delays

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±24mA Output drive current

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SCR-Latchup-resistant CMOS process and circuit design

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Green product and no Sb/Br