CD74ACT74M96E4

Flip Flop D-Type Pos-Edge 2Element 14Pin SOIC T/R

description/ordering information

The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset PRE or clear CLR inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive high, data at the data D input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

• Inputs Are TTL-Voltage Compatible

• Speed of Bipolar F, AS, and S, With

   Significantly Reduced Power Consumption

• Balanced Propagation Delays

• ±24-mA Output Drive Current

   – Fanout to 15 F Devices

• SCR-Latchup-Resistant CMOS Process and Circuit Design

• Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015