18兆位的DDR II + SRAM双字突发架构( 2.5周期读延迟) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency
SRAM - 同步,DDR II+ 存储器 IC 18Mb(512K x 36) 并联 165-FBGA(13x15)
立创商城:
CY7C11701KV18-400BZXC
贸泽:
SRAM 516K X 36 400MHz DDR II+ SRAM
艾睿:
SRAM Chip Sync Single 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin FBGA
Chip1Stop:
SRAM Chip Sync Single 1.8V 18M-bit 512K x 36 0.45ns 165-Pin FBGA Tray