36 - Mbit的QDR ? II + SRAM 4字突发架构( 2.0周期读延迟) 36-Mbit QDR? II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency
SRAM - 同步,QDR II+ 存储器 IC 36Mb(1M x 36) 并联 165-FBGA(13x15)
立创商城:
CY7C12451KV18-400BZXC
贸泽:
SRAM 1M X 36 400MHz QDR II+ SRAM
艾睿:
SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA Tray
Chip1Stop:
SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin FBGA Tray
Win Source:
36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency