36兆位的DDR -II + SRAM 2字突发架构( 2.5周期读延迟) 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency
SRAM - Synchronous, DDR II Memory IC 36Mb 4M x 8 Parallel 400MHz 165-FBGA 15x17
立创商城:
CY7C1268V18-400BZXC
得捷:
IC SRAM 36M PARALLEL 165FBGA
Chip1Stop:
SRAM Chip Sync Single 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin FBGA