CD74HC166

高速 CMOS 逻辑 8 位并行输入/串行输出移位寄存器

The ’HC166 and ’HCT166 8-bit shift register is fabricated with silicon gate CMOS technology. It possesses the low power consumption of standard CMOS integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky device.

The ’HCT166 is functionally and pin compatible with the standard ’LS166.

The 166 is an 8-bit shift register that has fully synchronous serial or parallel data entry selected by an active LOW Parallel Enable PE\\ input. When the PE\ is LOW one setup time before the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE\ is HIGH, data is entered into the internal bit position Q0 from Serial Data Input DS, and the remaining bits are shifted one place to the right Q0 → Q1 → Q2, etc. with each positive-going clock transition. For expansion of the register in parallel to serial converters, the Q7 output is connected to the DS input of the succeeding stage.

The clock input is a gated OR structure which allows one input to be used as an active LOW Clock Enable CE\\ input. The pin assignment for the CP and CE\ inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of CE\ input should only take place while the CP is HIGH for predictable operation.

A LOW on the Master Reset MR\\ input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a LOW state.

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Buffered Inputs

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Fanout Over Temperature Range

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Standard Outputs...10 LSTTL Loads

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Bus Driver Outputs...15 LSTTL Loads

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Wide Operating Temperature Range . . . -55°C to 125°C

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Balanced Propagation Delay and Transition Times

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Significant Power Reduction Compared to LSTTL Logic ICs

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HC Types

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2V to 6V Operation

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High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

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HCT Types

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4.5V to 5.5V Operation

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Direct LSTTL Input Logic Compatibility, VIL = 0.8V Max, VIH = 2V Min

Data sheet acquired from Harris Semiconductor