CD54HCT4024

高速 CMOS 逻辑 7 级二进制纹波计数器

The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

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Fully Static Operation

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Buffered Inputs

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Common Reset

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Negative Edge Clocking

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Fanout Over Temperature Range

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Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

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Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

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Wide Operating Temperature Range . . . -55°C to 125°C

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Balanced Propagation Delay and Transition Times

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Significant Power Reduction Compared to LSTTL Logic ICs

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HC Types

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2V to 6V Operation

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High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

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HCT Types

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4.5V to 5.5V Operation

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Direct LSTTL Input Logic Compatibility, VIL = 0.8V Max, VIH = 2V Min

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CMOS Input Compatibility, Il 1µA at VOL, VOH