CD54HC4060

带振荡器的高速 CMOS 逻辑 14 级二进制计数器

The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of O. All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.

In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.

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Onboard Oscillator

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Common Reset

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Negative Edge Clocking

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Fanout Over Temperature Range

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Standard Outputs . . . . 10 LSTTL Loads

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Bus Driver Outputs . . . . 15 LSTTL Loads

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Wide Operating Temperature Range . . . –55°C to 125°C

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Balanced Propagation Delay and Transition Times

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Significant Power Reduction Compared to LSTTL Logic ICs

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HC Types

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2V to 6V Operation

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High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

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HCT Types

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4.5V to 5.5V Operation

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Direct LSTTL Input Logic Compatibility, VIL = 0.8V Max, VIH = 2V Min

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CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor