CD74HC640

具有三态输出的高速 CMOS 逻辑八路反向总线收发器

The ’HC640 and ’HCT640 silicon-gate CMOS three-state bidirectional inverting and non-inverting buffers are intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high-speed operation when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuits, and have speeds comparable to low power Schottky TTL circuits. They can drive 15 LSTTL loads. The ’HC640 and ’HCT640 are inverting buffers.

The direction of data flow A to B, B to A is controlled by the DIR input.

Outputs are enabled by a low on the Output Enable input OE\\; a high OE\ puts these devices in the high impedance mode.

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Buffered Inputs

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Three-State Outputs

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Applications in Multiple-Data-Bus Architecture

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Fanout Over Temperature Range

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Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

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Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

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Wide Operating Temperature Range . . . -55°C to 125°C

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Balanced Propagation Delay and Transition Times

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Significant Power Reduction Compared to LSTTL Logic ICs

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HC Types

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2V to 6V Operation

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High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

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HCT Types

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4.5V to 5.5V Operation

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Direct LSTTL Input Logic Compatibility, VIL = 0.8V Max, VIH = 2V Min

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CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH