CDCM7005

高性能、低相位噪声、低偏移的时钟同步器（使参考时钟与 VCXO 同步）

The is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO voltage controlled crystal oscillator or VCO voltage controlled oscillator frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VCXO

VCXO_IN clock operates up to 2.2 GHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs PRI_REF and SEC_REF, supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, and input selection are programmable by SPI 3-wire serial peripheral interface. SPI allows individually control of the device settings.

The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.

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High Performance LVPECL and LVCMOS PLL

Clock Synchronizer

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Two Reference Clock Inputs Primary and

Secondary Clock for Redundancy Support With

Manual or Automatic Selection

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Accepts LVCMOS Input Frequencies up to 200

MHz

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VCXO_IN Clock is Synchronized to One of the

Two Reference Clocks

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VCXO_IN Frequencies Up to 2.2 GHz LVPECL

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Outputs Can Be a Combination of LVPECL and

LVCMOS Up to Five Differential LVPECL Outputs

or up to 10 LVCMOS Outputs

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Output Frequency is Selectable by ×1, /2, /3, /4,

/6, /8, /16 on Each Output Individually

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Efficient Jitter Cleaning From Low PLL Loop

Bandwidth

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Low Phase Noise PLL Core

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Programmable Phase Offset PRI_REF and

SEC_REF to Outputs

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Wide Charge Pump Current Range From

200 µA to 3 mA

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Dedicated Charge Pump Supply VCC_CP for

Wide Tuning Voltage Range VCOs

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Presets Charge Pump to VCC_CP/2 for Fast

Center-Frequency Setting of VCXO

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Analog and Digital PLL Lock Indication

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Provides VBB Bias Voltage Output for Single-

Ended Input Signals VCXO_IN

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Frequency Hold-Over Mode Improves Fail-Safe

Operation

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Power-up Control Forces LVPECL Outputs to 3-

State at VCC < 1.5 V

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SPI Controllable Device Setting

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3.3-V Power Supply

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Packaged in 64-Pin BGA 0.8 mm Pitch – ZVA or

48-Pin QFN RGZ

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Industrial Temperature Range –40°C to 85°C