DS90CR286AMTD

TEXAS INSTRUMENTS  DS90CR286AMTD  总线, CAN, 3 V, 3.6 V, TSSOP

The is a 3.3V Rising Edge Data Strobe LVDS Receiver converts the four LVDS data streams back into parallel 28-bits of LVCMOS data. The output of the receiver strobes on the rising edge. The receiver LVDS clock operates at rates from 20 to 66MHz. The device phase-locks to the input clock, samples the serial bit streams at the LVDS data lines and converts them into parallel output data. At an incoming clock rate of 66MHz, each LVDS input line is running at a bit rate of 462Mbps, resulting in a maximum throughput of 1.848Gbps. This device is an enhanced over prior generation receivers and provide a wider data valid time on the receiver output.

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Best-in-class set and hold times on RxOUTPUTs

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PLL requires no external components

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Compatible with A/EIA-644 LVDS standard

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<200µW Maximum Rx power-down mode

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50% Duty cycle on receiver output clock