5-43 MHz FPD 链接 LVDS（3 数据 + 1 时钟）至 FPD 链接 II LVDS（嵌入式时钟 DC 平衡转换器 36-WQFN
* 5 MHz–43 MHz Embedded Clock & DC-Balanced Data Transmission 21 Total LVDS Data Bits Plus 3 Low Speed LVCMOS Data Bits * User Adjustable Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable * Supports AC-Coupling Data Transmission * 100Ω Integrated Termination Resistor at LVDS Input * Power-Down Control * Available @SPEED BIST to DS90UR124 to Validate Link Integrity * All LVCMOS Inputs & Control Pins Have Internal Pulldown * Schmitt Trigger Inputs on OS[2:0] to Minimize Metastable Conditions * Outputs Tri-Stated Through DEN * On-Chip Filters for PLLs * Power Supply Range 3.3V ± 10% * Automotive Temperature Range −40°C to +105°C * Greater Than 8kV ESD Tolerance * Meets ISO 10605 ESD and AEC-Q100 Compliance
