DSP56311VF150R2

DSP Fixed-Point 24Bit 150MHz 150MIPS 196Pin MA-BGA T/R

Overview

The DSP56311 is designed with developers of multi-channel communication and networking systems in mind. With 300 million multiply accumulates per second MMACS operating performance, the 24-bit DSP56311 DSP offers excellent performance density characteristic of DSP56300 devices—maximizing the number of channels processed in a very small space while providing low power dissipation and excellent thermal performance at a competitive price. The DSP56311 maintains compatibility with all other DSP56300 devices, including application code, simulation models and system development tools.

The DSP56311 features the same enhanced filter coprocessor EFCOP found on the DSP56L307 to process filter algorithms such as echo cancelling and voice coding to run in parallel with the core. It is ideal for wireless and wireline infrastructure and Internet telephony applications where a single DSP handles several voice and data channels. Additional performance gains can be achieved through the use of the large on-chip RAM, thus reducing wait state penalty incurred when accessing external memory.

The DSP56311 uses split power supplies to separate the input/output I/O and peripheral sections, which operate at 3.3 volts, from the processor core, which runs at 1.8 volts. This approach allows the rest of the system to maintain a 3.3-volt external I/O environment while minimizing voltage and power dissipation in the chip internal logic.

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## Features

**High-performance DSP56300 core:**

* 150 MMACS 300 MIPS using the EFCOP in filtering applications with a 150 MHz clock at 1.8 volts

* Object code compatible with the DSP56000 core with highly parallel instruction set

* Data arithmetic logic unit data ALU with fully pipelined 24 x 24-bit parallel

* Multiplier-accumulator MAC, 56-bit parallel barrel shifter fast shift and normalization, bit stream generation and parsing, conditional ALU instructions and 24-bit or 16-bit arithmetic support under software control

* Program control unit PCU with position-independent code PIC support, addressing modes optimized for DSP applications including immediate offsets, on-chip instruction cache controller, on-chip memory-expandable hardware stack, nested hardware DO loops and fast auto-return interrupts

* Direct memory access DMA with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers including circular buffering; end-of-block- transfer interrupts; and triggering from interrupt lines and all peripherals

* Phase-lock loop PLL allows change of low-power divide factor DF without loss of lock

* Hardware debugging support including on-chip emulation OnCE module, JTAG test access port

**On-Chip Memories:**

* 128K on-chip RAM total program RAM, instruction cache, X data RAM and Y data RAM sizes are programmable:

**Program

RAM Size

.

*

|

**Instruction

Cache Size

.

*

**X Data

RAM Size

.

**

**Y Data

RAM Size

.

**

\---|---|---|---

32 K x 24-bit

0

48 K x 24-bit

48 K x 24-bit

31 K x 24-bit

1024 x 24-bit

96 K x 24-bit

16 K x 24-bit

16 K x 24-bit

95 K x 24-bit

1 6 K x 24-bit

16 K x 2 4-bit

80 K x 24-bit

24 K x 24-bit

24 K x 24-bit

79 K x 24-bit

64 K x 24-bit

32 K x 24-bit

63 K x 24-bit

40 K x 24-bit

40 K x 24-bit

47 K x 24-bit

* Includes 10 K x 24-bit shared memory i.e., memory shared by the core and the EFCOP.

* 192 x 24-bit bootstrap ROM

**Off-chip memory expansion:**

* Data memory expansion to two 256 K x 24-bit word memory spaces using standard external address lines

* Program memory expansion to one 256 K x 24-bit word memory space using standard external address lines

* External memory expansion port

* Chip select logic for glueless interface to SRAMs

**On-chip peripherals:**

* 3.3-volt I/O interface enhanced 8-bit parallel host interface HI08 supports a variety of buses for example, ISA and provides glueless connection to a number of industry-standard microcomputers, microprocessors and DSPs

* Two enhanced synchronous serial interfaces ESSI0 and ESSI1, each with one receiver and three transmitters

* Serial communications interface SCI with baud-rate generator

* Triple timer module

* Up to 34 programmable general-purpose I/O GPIO signals, depending on which peripherals are enabled

* Enhanced filter coprocessor EFCOP running in parallel with the core

**Reduced power dissipation:**

* Very low-power CMOS design

* Wait and stop low-power standby modes

* Fully static design specified to operate down to 0 Hz DC

* Optimized power management circuitry instruction-dependent, peripheral-dependent and mode-dependent

## Features