FIN1002M5X

FAIRCHILD SEMICONDUCTOR  FIN1002M5X  驱动器, LVDS, 差分接收, 1 ns, 7 mA, -40 °C, 85 °C, 3 V

The is a 1-bit Differential Receiver for high speed interconnects utilizing Low Voltage Differential Signalling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data. The FIN1002 can be paired with its companion driver or with any other LVDS driver.

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0.4ns Maximum differential pulse skew

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2.5ns Maximum propagation delay

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Bus pin ESD HBM protection exceeds 10kV

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Power-off overvoltage tolerant input and output

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Fail safe protection for open circuit and non-driven, shorted or terminated conditions

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High impedance output at VCC <1.5V

ESD sensitive device, take proper precaution while handling the device.