GAL16V8C-5LP

SPLD - 简单可编程逻辑器件 Use GAL16V8D

DESCRIPTION

The GAL16V8C, at 5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable E2 floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times <100ms allow the devices to be reprogrammed quickly and efficiently.

立创商城:
GAL16V8C-5LP

贸泽:
SPLD - 简单可编程逻辑器件 Use GAL16V8D

Win Source:
High Performance E2CMOS PLD Generic Array Logic