IS61LPS204818A-166TQL

SRAM Chip Sync Dual 3.3V 36M-Bit 2M x 18 3.5ns 100Pin TQFP

* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * Auto Power-down during deselect * Single cycle deselect * Snooze MODE for reduced-power standby * Power Supply: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% * JEDEC 100-Pin TQFP and 165-ball PBGA packages * Lead-free available