IS42S16320B-7TLI

INTEGRATED SILICON SOLUTION ISSI  IS42S16320B-7TLI  存储芯片, SDRAM, IND, 32M X 16, 3V, 54TSOP2

The is a 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as 8M x16x4 banks, 54-pin TSOPII and 54-ball W-BGA. The 512Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 536,870,912 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 134,217,728-bit bank is organized as 8,192 rows by 1024 columns by 16 bits. Each of the x8"s 134,217,728-bit banks is organized as 8,192 rows by 2048 columns by 8 bits. The 512Mb SDRAM includes an AUTO REFRESH MODE and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.

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143MHz Clock frequency

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7ns Speed

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Fully synchronous, all signals referenced to a positive clock edge

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Internal bank for hiding row access/precharge

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3.3V Vdd, 3.3V Vddq Single power supply

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LVTTL interface

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Programmable burst length - 1, 2, 4, 8, full page

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Sequential/Interleave programmable burst sequence

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Auto refresh CBR

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Self refresh

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8K Refresh cycles every 16ms A2 grade or 64ms commercial, industrial, A1 grade

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Random column address every clock cycle

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Programmable CAS latency - 2, 3 clocks

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Burst read/write and burst read/single write operations capability

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Burst termination by burst stop and precharge command