动态随机存取存储器 512M, 1.8V, 400Mhz 32M x 16 DDR2
SDRAM - DDR2 存储器 IC 512Mb（32M x 16） 并联 84-TWBGA（8x12.5）
得捷:
IC DRAM 512MBIT PARALLEL 84TWBGA
贸泽:
动态随机存取存储器 512M, 1.8V, 400Mhz 32M x 16 DDR2
艾睿:
DRAM Chip DDR2 SDRAM 512Mbit 32Mx16 1.8V 84-Pin TW-BGA T/R
安富利:
ISSI"s 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed BA0-BA1 select the bank; A0-A12x16 or A0-A13x8 select the row. The address bits registered coincident with the Read or Write command are used to select the starting column location A0-A9 for the burst access and to determine if the auto precharge A10 command is to be issued. Prior to normal operation, the DDR2 SDRAM must be
Win Source:
IC DDR2 512MB 400MHZ CL5 84BGA