ISPLSI1024EA-100LT100

EE PLD, 12.5ns, 96-Cell, CMOS, PQFP100, TQFP-100

Description

The ispLSI 1024EA is a High Density Programmable Logic Device containing 144 Registers, 48 Universal I/O pins, two Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool GRP. The GRP provides complete interconnectivity between all of these elements. The ispLSI 1024EA features 5V in-system diagnostic capabilities via IEEE 1149.1 Test Access Port.

The ispLSI 1024EA device offers non-volatile reprogrammability of the logic, as well as the intercon nects to provide truly reconfigurable systems. A functional superset of the ispLSI 1024 architecture, the ispLSI 1024EA device adds user selectable 3.3V or 5V I/O and open-drain output options.