ISPLSI2032VE-110LTN48

EE PLD, 13ns, 32-Cell, CMOS, PQFP48, 7 X 7MM, 0.5MM PITCH, LEAD FREE, TQFP-48

Description

The ispLSI 2032VE is a High Density Programmable Logic Device that can be used in both 3.3V and 5V systems. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool GRP. The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032VE features in-system programmability through the Boundary Scan Test Access Port TAP and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2032VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

Features

• SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC

   — 1000 PLD Gates

   — 32 I/O Pins, Two Dedicated Inputs

   — 32 Registers

   — High Speed Global Interconnect

   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

   — Small Logic Block Size for Random Logic

   — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V Devices

• 3.3V LOW VOLTAGE 2032 ARCHITECTURE

   — Interfaces With Standard 5V TTL Devices

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

   — fmax = 300 MHz Maximum Operating Frequency

   — tpd = 3.0 ns Propagation Delay

   — Electrically Erasable and Reprogrammable

   — Non-Volatile

   — 100% Tested at Time of Manufacture

   — Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

   — 3.3V In-System Programmability Using Boundary Scan Test Access Port TAP

   — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic

   — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality

   — Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

   — Enhanced Pin Locking Capability

   — Three Dedicated Clock Input Pins

   — Synchronous and Asynchronous Clocks

   — Programmable Output Slew Rate Control

   — Flexible Pin Placement

   — Optimized Global Routing Pool Provides Global Interconnectivity

   — Lead-Free Package Options