JM38510/65302B2A

双D型上升沿触发的触发器具有清零和预设 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

description/ordering information

The ’HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset PRE or clear CLR inputs sets or resets the outputs, regardless of the levels of the other inputs. When PREand CLRare inactive high, data at the data D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock CLK pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 40-µA Max ICC

Typical tpd = 15 ns

±4-mA Output Drive at 5 V

Low Input Current of 1 µA Max