vivado----fpga硬件调试 (五) ----找不到ila核问题及解决方案
INFO: [Labtools 27-2302] Device xczu9 (JTAG device index = 0) is programmed with a design that has 2 ILA core(s). WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/example_stimulus_inst0/ila_inst' at location 'uuid_41FD5F9F348352C49809B95E968FAEB2' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/example_checking_inst0/ila_inst' at location 'uuid_6B51478F60F05E37813EC1672C3407E4' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/system_wrapper_i/system_i/system_ila_0/inst/ila_lib' at location 'uuid_8C077A2A8ACC5CC2BB3FE9F1AD28CC92' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/system_wrapper_i/system_i/system_ila_1/inst/ila_lib' at location 'uuid_8D89719A73C25B1C852609031899D29D' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/ila_inst' at location 'uuid_BBBF989AD10F59A191B44CF3E0FBBFD2' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/GTH_TX_RX_vio_0_inst' at location 'uuid_DE37F6E204CA542FB479630A93889915' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xczu9_0 and the probes file(s) F:/TLK2711_GTH_serial_to_parallel/project/01dma_ps_base_2711/zu_prj/zu_prj.runs/impl_1/top.ltx. The device design has 2 ILA core(s) and 0 VIO core(s). 0 ILA core(s) and 0 VIO core(s) are matched in the probes file(s). Resolution: 1. Reprogram device with the correct programming file and associated probes file(s) OR 2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device. open_bd_design {F:/TLK2711_GTH_serial_to_parallel/project/01dma_ps_base_2711/zu_prj/zu_prj.srcs/sources_1/bd/system/system.bd}
个人情况用例程ila调试界面信号和波形可在下载程序后弹出。查了原因后，我查了设计中使用的时钟zynq PS可使用端提供的输出时钟，以满足解释的原因。在这个设计的基础上加入自己的东西后，调试界面什么都没有。根据时钟的原因，猜测我的时钟用错了，所以没有图形。最后的结果是我用了simulation试了一下，简单的模拟板也有问题，所以根据问题我改了代码，关掉基本的模拟，然后下板debug核出来了。以下是发现的原因。
vivado----fpga硬件调试 (五) ----找不到ila核问题及解决方案_坚持-CSDN博客
用这个链接的答案，但是恐怕有一天会消失，所以复制一下
也许设计中没有ILA core，但是debug文件里有ILA core，而且debug probes窗户下面什么都没有。然而，我在综合后显然插入了它debug core啊，相关信息在约束文件中自动生成schematic，也添加了debug两个相关元件是毛program就是看不见？
不知道有没有人遇到过类似的情况，求指点，非常感谢！
解决：
1： VIO 和 ILA 的CLK 有问题。
2： 我查的Xilinx看来论坛也是这么说的，说要用free running clock，但我不明白什么样的名字叫我free running clock。我用的是寄存器的原始时钟。如果换个时钟，怎么能保证采样不会有问题？还是不太懂，能详细指导吗？
所谓的free running clock是上电时跑的时钟，而不是依靠某些条件。补充一点，FREE CLOCK确实需要无条件上电的时钟。有一次遇到一种情况。用MMCM或者PLL输出时钟作为采样时钟，但如果MMCM或者PLL这个输入不是电源，而是等待FPGA程序运行后，时钟输入来了，所以下载程序后还是ILA调试界面没有信号。把MMCM或者PLL输入时钟改为晶振时钟，可正常使用ILA了。这是我个人的感觉，没有经过很多验证，所以我希望你能给我更多的建议。补充一点，FREE CLOCK确实需要无条件上电的时钟。
其实不用FREE CLOCK也没问题。比如用ZYNQ PS产生的CLK也可以。上电后做PS初始化，然后设置所需的寄存器，然后更新DEVICE，就可以找到ILA了。
3 ： 我遇到过这个问题。事实上，第一种情况是你的时钟信号可能没有成功添加（例如，外部输出时钟信号没有进入或范围太小，内部时钟可能没有lock）；第二种情况是你输入ila核的时钟频率不合适。其实，ila它是一个你需要检查的信号，所以最好直接使用外部mmcm产生比您需要收集信号的最高频率更多的采样（具体频率取决于您对采样点的需求和您的信号频率）。
4： 这个问题是时钟造成的。当bit file program完成之后，fpga/vivado会自动检测ila的clock如果不存在，是否存在pll/mmcm没有lock)，它就会report 这个warning。这时，我们只需要让时钟工作，refresh一下device，ila就会启动--ila窗户会出来。
5 ： 试着直接使用外部输入的时钟(可以通过时钟)buf）作为ila的clk，不要使用其他模块产生的时钟。
问题 二：
我在vivado下调试，调用ILA IP Core。如果ila以晶振输入为例clk时（也即全局时钟），在顶层RTL等级，可见ila连接数据和时钟。Debug时也能在Hardware下看到XADC和ILA。 但如果ila的clk，分频后使用逻辑计数的时钟信号，或使用clock wizard倍频后的时钟信号。RTL下看ILA的clk与上述时钟源没有连接。bit流下载后Debug，也只能看到XADC而看不到ILA核。 想知道使用ILA时，ila的clk输入源是否有特殊限制？
解决：
1 ： 难道是：（Xilinx PG172） The clk input port is the clock used by the ILA core to register the probe values. For best results, it should be the same clock signal that is synchronous to the design logic that is attached to the probe ports of the ILA core.
2 ： 首先确保你的分频结果是有效的。 然后，如果你非要用分频结果的话，过一个bufg试试。
// BUFG: 全局时钟缓存（Global Clock Buffer），只能以内部信号驱动 // Xilinx HDL库向导版本，ISE 9.1 BUFG BUFG_inst ( .O(O), //时钟缓存输出信号 .I(I) // /时钟缓存输入信号 ); // 结束BUFG_ins模块的例化过程
还有一个原因出在JTAG下载线上，有些山寨厂家做的下载线不好，不能检测到ILA核。更换下载器之后就变好了。这个原因我觉得能够通过对比其他程序能够测试出来，像我这个有标准例程，例程可以弹出来，自己设计的弹不出来，那就和下载线没关系了。
20220331
调试另一个工程时又遇到了类似问题，这次的报错有相同之处也有不一样的地方，开始的时候报如下错误。而且这次连波形界面都没弹出来，直接需要refresh program 也不管用
INFO: [Labtools 27-1434] Device xczu9 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3361] The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/system_wrapper_i/system_i/system_ila_2/inst/ila_lib' at location 'uuid_0E830E21B812559795505962EE4B3A99' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/system_wrapper_i/system_i/system_ila_1/inst/ila_lib' at location 'uuid_40E5594B98DC574CA0305310E38B3046' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/GTH_TX_RX_vio_0_inst' at location 'uuid_51B529683A64508994A8DAE8350AE2C4' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/system_wrapper_i/system_i/system_ila_4/inst/ila_lib' at location 'uuid_84CCF78622E25DB0852CA9D4E61984DF' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/system_wrapper_i/system_i/ila_0' at location 'uuid_A2CC5A5037325DB7B7872C856D4721A0' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/example_checking_inst0/ila_inst' at location 'uuid_A7235B8C450152DC9BF1C3FFC37AE103' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/system_wrapper_i/system_i/system_ila_3/inst/ila_lib' at location 'uuid_B3145229BC605C49A15B44CD96780C6F' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/system_wrapper_i/system_i/system_ila_0/inst/ila_lib' at location 'uuid_C461DBF56F9058BD83091D2778CED044' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ps_2711_loop/ila_inst' at location 'uuid_FED39276B86A5F4EACCCD58E302522CB' from probes file, since it cannot be found on the programmed device. refresh_hw_device [lindex [get_hw_devices xczu9_0] 0]
这个错误我找了资料和前面基本一致，就是之前的还有一部分调试核，这个没有调试核，所以一直没找到我到底哪里错了。但得到了一点启发是综合后打开open synthesized design ---> set up debug 因为我是在BD里面加得ila核，所以其实没用到这个地方，但还是打开看了一下，结果报出了下面的警告critical warning 才给了我提示。
[Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports hb_gtwiz_reset_clk_freerun_in]'. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:80] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. [Vivado 12-1419] Debug core 'u_ila_1' was not found. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:110] [Vivado 12-1419] Debug core 'u_ila_3' was not found. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:112] [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:164] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:165] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:166] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:167] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:168] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:169] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:170] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:171] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:172] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:173] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:174] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:175] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:176] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:177] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:178] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. [Common 17-55] 'set_property' expects at least one object. [F:/TLK2711_GTH_serial_to_parallel/project/02_dma_ps_loop_2711/zu_prj/zu_prj.srcs/constrs_1/imports/imports/GTH_TX_RX_example_top.xdc:179] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
这一堆就可以定位到问题出在了xdc文件里面，因为这个文件是从其他工程里拷贝过来的，所以有些自动生成的Mark——debug 的路径还是原来工程的，而我的工程已经换了，所以需要把路径都改过来。改完后发现报的错依然没变，所以不是这的问题，后来发现一个复位信号搞错了。所以把复位信号改过来再试试，试完后依然没效果，然后第二天才想起来之前就是simulation的时候就有问题，所以这次又simulation了一下，发现确实连时钟信号都没有，所以先不用下板调试了，先过了simulation这关后再下板调试估计会好。
simulation后确实发现了些问题，有些复位信号移植的时候没改，有的没有了还在上面，于是都改过来了，但是依然没解决问题。想起了上次的原因是工程没设置成顶层，set up top ,simulation也是，都设置成顶层后就弹出来波形了。这次的却没找到原因呢，各种更改代码，发现了好多代码问题，改完后还是不行，报同样的错误，最后利用排除法，排除了一部分工程，通过上面的链接仔细研读，确认应该就是我自己设置的时钟出现的问题。PS到PL的过程中通过fifo，fifo输入的时钟是PS-PL时钟，FIFO输出时钟是我PL端的时钟，因为一直用的assign赋值语句，所以认为自己PL端的时钟都是统一的，理论上不应该出现问题。但因为确认了是时钟问题，所以再次观察simulation波形每一步的时钟，然后发现了一些蛛丝马迹。原来的PL到PS的工程成功了。我自己造的激励，是起始时钟，来源于GTH，然后传输到PS端。但现在的工程顺序变了。是PS端产生激励数据，然后传出到PL端。而这个时钟是通过赋值语句得到了，有一定的延时，通过如下波形才恍然醒悟。
最终通过逻辑理解这个时钟不可以比GTH的延迟或者慢，因为它是始发时钟，所以把GTH输出时钟直接赋值给s_axis_aclk，看看好没好，结果是弹出了瞬间的框又消失了。所以思路应该没问题，下周继续照着这个思路调试。
20220406
历经四整天（中间休息了，工作日四整天），终于在我彻底绝望的情况下，出来调试核界面了。真的是。。。。
上面的思路试了以后依然报错，但错误里多了几行这样的警告
- WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped
然后一查，还是同样的解释，我真的彻底绝望了，本来觉得排除法猜测出了就是时钟的原因，但改完了也不行，后来又发现行信号，一行的个数我这里是512，设置错了，改了过来也不行。最后我彻底没希望了。按照大家的解释，把输入时钟改成了自由时钟，free-clock的assign的时钟，再试一下，结果成功了，但总觉得不合适，但不管那么多了，至少出来了调试界面，看到调试信号才能知道错在哪里。。。
20200407
最终确认我原始设计的参考时钟因为是输出时钟，在设置不对的情况下，无时钟信号，所以一直无法弹出波形，通过自由时钟弹出波形后发现的时钟一直没有，所以是设计有问题，改好后，时钟有了，将原本改成自由时钟做参考时钟的设计换回我需要的输出参考时钟后波形也有了。所以结论是。我这个设计有问题，参考时钟不对，没出来，所以一直弹不出调试界面来。