先放我们的实验要求。实验要求不一样的话，慎重参考。
源程序：
//总模块
module FrequencyCounter(
input [1:0] testmode ,
input sysclk ,
input modecontrol,
output
highfreq,
output [6:0] hex0,
output[6:0] hex1,
output[6:0] hex2,
output[6:0] hex3
);
wire sigin11;
assign highfreq=modecontrol;
signalinput signalin(.testmode(testmode),.sysclk(sysclk),.sigin1(sigin11));
Frequency freq(.sigin11(sigin11),.sysclk(sysclk),.modecontrol(modecontrol),.hex0(hex0),.hex1(hex1),.hex2(hex2),.hex3(hex3));
endmodule
//频率计模块
module Frequency(sigin11,sysclk,modecontrol,hex0,hex1,hex2,hex3);
input sigin11,sysclk,modecontrol;
// output
highfreq;
output [6:0]hex0,hex1,hex2,hex3;
wire [15:0]countBCD;
wire [15:0]locker;
wire OneClk;
wire enable,reset,lock,sigin12;
//signalinput siginai(.testmode(testmode),.sysclk(sysclk),.sigin1(sigin11));
OneHzClk onehz(.sysclk(sysclk),.OneClk(OneClk));
ControlSig controls(.OneClk(OneClk),.enable(enable),.reset(reset),.lock(lock));
TenDivideFre tendiv(.sigin(sigin11),.sigin1(sigin12));
TenCounter tencou(.sigin(sigin11),.sigin1(sigin12),.modecontrol(modecontrol),.enable(enable),.reset(reset),.countBCD(countBCD));
lockMachine lockma(.lock(lock),.countBCD(countBCD),.locker(locker));
ShuMa shum(.locker(locker),.hex0(hex0),.hex1(hex1),.hex2(hex2),.hex3(hex3));
endmodule
//siginal Input Module
module signalinput(
input [1:0] testmode,//00,01,10,11????4???????3125?250?50?12500Hz???SW1~SW0???
input sysclk,//????50M
output sigin1//??????
);
reg[20:0] state;
reg[20:0] divide;
reg sigin;
assign sigin1=sigin;
initial
begin
sigin=0;
state=21'b000000000000000000000;
divide=21'b0000000_1111_1010_000000;
end
always@(testmode) begin
case(testmode[1:0])
2'b00:divide=21'b0000000_1111_1010_000000;
//3125Hz
2'b01:divide=21'b00000000_1111_1010_00000;
//6250Hz
2'b10:divide=21'b01111_0100_0010_0100_0000;//50Hz
2'b11:divide=21'b00000_0000_1111_1010_0000;
//12500Hz
endcase
end
always@(posedge sysclk)//?divide??
begin
if(state==0)
sigin=~sigin;
state=state+21'b0_00__0000_0000_0000_0000_10;
if(state==divide)
state=27'b000_0000_0000_0000_0000_0000_0000;
end
endmodule
//1Hz clock module
module OneHzClk(sysclk,OneClk);
reg[25:0] state;
reg[25:0] divide;
input sysclk;
output
OneClk;
reg sigin;
assign OneClk=sigin;
initial
begin
sigin=0;
state=26'b00_0000_0000_0000_0000_0000;
divide=26'b10_1111_1010_1111_0000_1000_0000;
//divide=21'b000000_0000_0000_0001000;
end
always@(posedge sysclk)//?divide??
begin
if(state==0)
sigin=~sigin;
state=state+26'b0000_0000__0000_0000_0000_0000_10;
if(state==divide)
state=26'b00_0000_0000_0000_0000_0000_0000;
end
endmodule
//1Hz clk produce control siginal
module ControlSig(OneClk,enable,reset,lock);
input wire OneClk;
output reg enable,reset,lock;
reg countcc;
initial begin
enable=0;
reset=1;
lock=0;
countcc=0;
end
always@(posedge OneClk)
begin
countcc=countcc+1;
if(countcc==0)
begin
lock=0;
reset=1;
enable=1;
end
else if(countcc==1)
begin
lock=1;
reset=0;
enable=0;
end
end
endmodule
//10 counter module
module TenCounter(sigin,sigin1,modecontrol,enable,reset,countBCD);
input wire sigin,sigin1,modecontrol,enable,reset;
output [15:0] countBCD;
wire sigi;
assign sigi=modecontrol?sigin1:sigin;
reg [3:0]count0,count1,count2,count3;
assign countBCD[3:0]=count0;
assign countBCD[7:4]=count1;
assign countBCD[11:8]=count2;
assign countBCD[15:12]=count3;
initial begin
count0=4'b0000;
count1=4'b0000;
count2=4'b0000;
count3=4'b0000;
end
always@(posedge sigi or negedge reset)
begin
if(!reset)
begin
count0=4'b0000;
count1=4'b0000;
count2=4'b0000;
count3=4'b0000;
end
else
源程序：
//总模块
module FrequencyCounter(
input [1:0] testmode ,
input sysclk ,
input modecontrol,
output