先放实验要求：
实验源程序：
module FrameSyn(stateout,dataouten,datawrong,reset,system_clk,mode);
output reg [3:0] stateout;
output dataouten,datawrong;
input [1:0] mode;
input reset,system_clk;
wire [1:0] state;
wire clk,datain,dataout;
always @(state)
begin
case (state)
2'b00 : stateout = 4'b0001;
2'b01 : stateout = 4'b0010;
2'b10 : stateout = 4'b0100;
2'b11 : stateout = 4'b1000;
endcase
end
FrameSynM FrameSM0(.state(state), .dataout(dataout), .dataouten(dataouten), .reset(reset), .clk(clk), .datain(datain));
FrameDataCheck FrameDataCheck0(.Reset(reset), .Clock(clk), .DataOut(dataout), .DataOutEn(dataouten), .DataWrong(datawrong));
FrameTrans FrameTrans0(.Reset(~reset), .Clock100M(system_clk), .Mode(mode), .Clock(clk), .DataIn(datain));
endmodule
module FrameSynM(state,dataout,dataouten,reset,clk,datain);
output reg [1:0] state;
output reg dataouten;
output dataout;
input datain,clk,reset;
reg [7:0] data_count;
reg [7:0] frame;
reg [1:0] matchtimes,mismatchtimes;
assign dataout = datain;
always @(negedge reset or posedge clk)
begin
if (!reset)
begin
state <= 2'b00;
frame <= 8'b0000_0000;
data_count <= 8'b0000_0000;
matchtimes <= 2'b00;
mismatchtimes <= 2'b00;
dataouten <= 0;
end
else
begin
frame <= {frame[6:0], datain};
if (state == 2'b00)
begin
if (frame == 8'b1001_1011)
begin
data_count <=0;
matchtimes <= matchtimes + 1;
mismatchtimes <= 2'b00;
end
else
begin
实验源程序：
module FrameSyn(stateout,dataouten,datawrong,reset,system_clk,mode);