再编十进制74LS290，项目名定为CTLS290：
library ieee; use ieee.std_logic_1164.all; entity CTLS290 is port(clk0:in std_logic; S91,S92,R01,R02:in std_logic; Q0,Q1,Q2,Q3:out std_logic); end CTLS290; architecture court of CTLS290 is
signal tmp0,tmp1,tmp2,tmp3:std_logic;
signal a,b,Sd0,Rd0,Rd1,Rd2,Sd3,Rd3:std_logic; component Dff_JK_111 port( J,K:in std_logic; clk,Rd,Sd:in std_logic; Q:out std_logic); end component; begin a<=not(S91 and S92);b<=not(R01 and R02); Rd0<=b;Sd0<=a; Rd1<=a and b;Rd2<=a and b;
Rd3<=b;Sd3<=a; U0:Dff_JK_111 port map('1','1',clk0,Rd0,Sd0,tmp0); U1:Dff_JK_111 port map((not tmp3),'1',tmp0,Rd1,'1',tmp1); U2:Dff_JK_111 port map('1','1',tmp1,Rd2,'1',tmp2); U3:Dff_JK_111 port map((tmp1 and tmp2),'1',tmp0,Rd3,Sd3,tmp3); Q0<=tmp0;Q1<=tmp1;Q2<=tmp2;Q3<=tmp3; end court;
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