不带使能端的3线8线译码器：
1。用CASE语句
LIBRARY E;
USE IEEE.D_LOGIC_1164.ALL;
EITY LS138 IS
PORT ( S:in STD_LOGIC_vector(2 downto 0);
Y: out STD_LOGIC_vector(7 downto 0));
end LS138;
ARCHICTURE mux_behave OF LS138 IS
begin
PROCESS(S) IS
BEGIN
CASE S IS
when "000"=>Y<=(0=>'0',S=>'1');
when "001"=>Y<=(1=>'0',OTHERS=>'1');
when "010"=>Y<=(2=>'0',OTHERS=>'1');
when "011"=>Y<=(3=>'0',OTHERS=>'1');
when "100"=>Y<=(4=>'0',OTHERS=>'1');
when "101"=>Y<=(5=>'0',OTHERS=>'1');
when "110"=>Y<=(6=>'0',OTHERS=>'1');
when "111"=>Y<=(7=>'0',OTHERS=>'1');
END CASE;
END PROCESS;
end mux_behave;
2。用公式
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTY yimaqi138 IS PORT (A,B,C:IN STD_LOGIC; S1,notS2,notS3:IN STD_LOGIC; Y0,Y1,Y2,Y3: out STD_LOGIC; Y4,Y5,Y6,Y7: OUT STD_LOGIC); End yimaqi138; ARCHITECTURE mux_behave OF yimaqi138 IS SIGNAL S:STD_LOGIC; BEGIN S<=S1 AND (NOT notS2) AND (NOT notS3); Y0<=NOT(((NOT A)AND(NOT B)AND (NOT C)) AND S); Y1<=NOT(((NOT A)AND (NOT B) AND C)AND S); Y2<=NOT(((NOT A) AND B AND (not C))AND S); Y3<=NOT(((NOT A) AND B AND C )AND S); Y4<=NOT((A AND(NOT B)AND (NOT C))AND S); Y5<=NOT((A AND (NOT B) AND C)AND S); Y6<=NOT((A AND B AND (not C))AND S); Y7<=NOT((A AND B AND C )AND S); end mux_behave;
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