SN74ABT16373A

具有三态输出的 16 位透明 D 类锁存器

The "ABT16373A are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable LE input is high, the Q outputs follow the data D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable OE\\ input can be used to place the eight outputs in either a normal logic state high or low logic levels or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16373A is characterized for operation over the full military temperature range of -55°C to 125°C. The is characterized for operation from -40°C to 85°C.

.

Members of the Texas Instruments **_Widebus_**TM Family

.

State-of-the-Art **_EPIC-_**II **_B_**TM BiCMOS Design Significantly Reduces Power Dissipation

.

Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17

.

Typical V**OLP** Output Ground Bounce < 0.8 V at V**CC** = 5 V, T**A** = 25°C

.

High-Impedance State During Power Up and Power Down

.

Distributed V**CC** and GND Pin Configuration Minimizes High-Speed Switching Noise

.

Flow-Through Architecture Optimizes PCB Layout

.

High-Drive Outputs -32-mA I**OH**, 64-mA I**OL**

.

Package Options Include Plastic 300-mil Shrink Small-Outline DL and Thin Shrink Small-Outline DGG Packages and 380-mil Fine-Pitch Ceramic Flat WD Package Using 25-mil Center-to-Center Spacings

Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.