MC100EP195B 系列 3.3 V ECL 可编程延时芯片 - QFN-32
The MC100EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195B has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D9:0 values and controlled by the LEN pin 10. A LOW level on LEN allows a transparent LOAD mode of real time delay values by D9:0. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D10:0. The approximate delay values for varying tap numbers correlating to D0 LSB through D9 MSB are shown in Table 6 and Figure 3.
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型号 | 品牌 | 下载 |
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MC100EP195BMNR4G | ON Semiconductor 安森美 | 下载 |
MC100EP195FAG | ON Semiconductor 安森美 | 下载 |
MC100EP196FAG | ON Semiconductor 安森美 | 下载 |
MC100EP195BMNG | ON Semiconductor 安森美 | 下载 |
MC100EP195MNG | ON Semiconductor 安森美 | 下载 |
MC10EP195FAG | ON Semiconductor 安森美 | 下载 |
MC10EP195MNR4G | ON Semiconductor 安森美 | 下载 |
MC100EL15DG | ON Semiconductor 安森美 | 下载 |
MC100EP32DTG | ON Semiconductor 安森美 | 下载 |
MC100LVEL11DTG | ON Semiconductor 安森美 | 下载 |
MC100LVEP11DG | ON Semiconductor 安森美 | 下载 |