DS90LT012AQMF/NOPB

LVDS 接口集成电路 Auto LVDS Diff Line Receiver

The is a single CMOS differential Line Receiver designed for applications requiring ultra-low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400Mbps 200MHz utilizing low voltage differential swing LVDS technology. It accepts low voltage 350mV typical differential input signals and translates them to 3V CMOS output levels. It includes an input line termination resistor for point-to-point applications. The DS90LT012AQ and companion LVDS line driver DS90LV011AQ provide a new alternative to high power PECL/ECL devices for high speed interface applications.

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Integrated line termination resistor 100R typical

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Power down high impedance on LVDS inputs

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LVDS inputs accept LVDS/CML/LVPECL signals

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Pin-out simplifies PCB layout

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>400Mbps 200MHz Switching rate

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100ps Differential skew typical

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3.5ns Maximum propagation delay

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10mW at 3.3V static Typical low power dissipation

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Green product and no Sb/Br