PC16552DV

TEXAS INSTRUMENTS  PC16552DV  接口, UART, 2通道, 4.5 V, 5.5 V, LCC, 44 引脚

The is an Universal Asynchronous Receiver/Transmitter UART features that two serial channels are completely independent except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the 16450. Each channel can operate with on-chip transmitter and receiver FIFOs FIFO mode to relieve the CPU of excessive software overhead. In FIFO mode each channel is capable of buffering 16 bytes plus 3-bits of error data per byte in the RCVR FIFO of data in both the transmitter and receiver. All the FIFO control logic is on-chip to minimize system overhead and maximize system efficiency. Signalling for DMA transfers is done through two pins per channel TXRDY# and RXRDY#. The RXRDY# function is multiplexed on one pin with the OUT 2# and BAUDOUT functions. The CPU can select these functions through a new register Alternate Function Register. Each channel performs serial-to-parallel conversion on data characters.

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Dual independent UARTs

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Capable of running all existing 16450 and PC16550D software

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After reset, all registers are identical to the 16450 register set

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Read and write cycle times of 84ns

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Independently controlled transmit, receive, line status and data set interrupts

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MODEM control functions CTS, RTS, DSR, DTR, RI and DCD

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Even, odd or no-parity bit generation and detection

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False start bit detection

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Complete status reporting capabilities

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TRI-STATE® TTL drive for the data and control buses

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Line-break generation and detection

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Loopback controls for communications link fault isolation

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Break, parity, overrun and framing-error simulation

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Full prioritized interrupt system controls

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Can also be reset to 16450 Mode under software control