SRAM Chip Sync Quad 2.5V 18M-Bit 512K x 36 6.5ns 100Pin TQFP
* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single R/W Read/Write control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Power Down mode * Common data inputs and data outputs * /CKE pin to enable clock and suspend operation * JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages * Power supply * Vdd 2.5V ± 5%, Vddq 2.5V ± 5% * JTAG Boundary Scan for BGA packages * Commercial and Industrial temperature support * Lead-free available.
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