CY6264-70SNXC

CYPRESS SEMICONDUCTOR  CY6264-70SNXC  芯片, 存储器, SRAM, 64KB, 并行口, 70NS NSOIC28

SRAM - 异步 存储器 IC 64Kb（8K x 8） 并联 70 ns 28-SOIC

得捷:
IC SRAM 64KBIT PARALLEL 28SOIC

贸泽:
静态随机存取存储器 64Kb 5V 70ns 8K x 8 静态随机存取存储器

e络盟:
CYPRESS SEMICONDUCTOR  CY6264-70SNXC  芯片, 存储器, SRAM, 64KB, 并行口, 70NS NSOIC28

艾睿:
SRAM Chip Async Single 5V 64K-Bit 8K x 8 70ns 28-Pin SNC N Tube

安富利:
SRAM Chip Async Single 5V 64K-Bit 8K x 8 70ns 28-Pin SNC N

Chip1Stop:
SRAM Chip Async Single 5V 64K-Bit 8K x 8 70ns 28-Pin SNC N Tube

Verical:
SRAM Chip Async Single 5V 64K-bit 8K x 8 70ns 28-Pin SNC N Tube

Newark:
The CY6264-70SNXC is a 8k high-performance CMOS static RAM organized as 8192 words by 8-bits. Easy memory expansion is provided by an active LOW chip enable, an active HIGH chip enable and active LOW output enable and 3-state drivers. Both devices have an automatic power-down feature reducing the power consumption by over 70% when deselected. An active LOW write enable signal controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins, is written into the memory location addressed by the address present on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.

Win Source:
IC SRAM 64KBIT 70NS 28SOIC

DeviceMart:
IC SRAM 64KBIT 70NS 28SOIC