SN74SSTV16859RGQ8

13位到26位寄存缓冲器与SSTL 2输入和输出 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset RESET\ input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV16859 operates from a differential clock CLK and CLK\\\\. Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven floating data, clock, and reference voltage VREF inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.