CK-V7-VC7222-G-J

表征套件, Virtex-7 FPGA, IBERT, Vivado, 仅限日本

The from is a Virtex-7 FPGA VC7222 characterization kit Japan specific. The kit provides the hardware environment for characterizing and evaluating the GTH and GTZ transceivers available on the Virtex-7 XC7VH580T-G2HCG1155E FPGA while allowing evaluation of the Integrated Bit Error Ratio Test IBERT demonstration using the Vivado® Design Suite. Each GTH and GTZ Quad and its associated reference clock are routed from the FPGA to SMA and Samtec BullsEye connector. A cable containing a BullsEye connector and standard SMA connectors allows users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTH or GTZ quad, four transmit/receive pairs, enabling the highest level of flexibility in testing custom applications.

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Hardware, design tools, IP and pre-verified reference designs

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Integrated Bit Error Ratio Test IBERT reference design

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System ACE™ SD controller, 580480 logic cell, 1680 DSP slices

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Expand I/O with 2 FPGA Mezzanine Card FMC interface

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BullsEye connector supporting a full GTH or GTZ quad with four transmit/receive pairs

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Six Samtec BullsEye connector pads for the GTH transceivers and reference clocks

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Two pairs of differential MRCC inputs with SMA connectors

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Two Samtec BullsEye connector pads for the GTZ transceivers and reference clocks

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Power status LEDs and general purpose DIP switches, LEDs, push buttons and test I/O display

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SuperClock-2 module supporting multiple frequencies, 33840Kb memory