CDCUN1208LPRHBT

400 MHz的低功耗2 ： 8扇出缓冲器 400 MHz Low Power 2:8 Fan-Out Buffer

The is a 2:8 Fan-out Buffer featuring a wide operating supply range, two universal differential/single-ended inputs and universal outputs HCSL, LVDS or LVCMOS with edge rate control. The clock buffer supports PCIE gen1, gen2 and gen3. One of the device inputs includes a divider that provides divide values of 1, 2, 4 or 8. It is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, it provides a SPI/I²C port with which a host processor controls device settings. It delivers excellent additive jitter performance and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.

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Support PCIE gen1, gen2, gen3

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Low power consumption and power management

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1.8V Operation and output enable control

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Integrated voltage regulators improve PSNR

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Excellent additive jitter performance

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Green product and no Sb/Br

Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.