74AC11138

3 线路至 8 线路解码器/多路解复用器

The circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select A, B, C inputs and the three enable G1, , inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The 74AC11138 is characterized for operation from -40°C to 85°C.

 

 

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Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems

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Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception

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Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

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EPICTM Enhanced-Performance Implanted CMOS 1-m Process

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500-mA Typical Latch-Up Immunity at 125°C

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Package Options Include Plastic Small-Outline D and Thin Shrink Small-Outline PW Packages, and Standard Plastic 300-mil DIPs N

 

EPIC is a trademark of Texas Instruments Incorporated.