TEXAS INSTRUMENTS CD40103BE 芯片, 逻辑芯片 - 4000系列, 计数器
The is a 8-stage 8-bit presettable CMOS Binary Synchronous Down Counter with a single output which is active when the internal count is zero. It has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the carry-out/zero-defect output is active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the carry-in/counter enable CI/CE\\ input is high. The carry-out/zero-defect CO/ZD\\ output goes low when the count reaches zero if the CI/CE\ input is low and remains low for one full clock period. When the synchronous preset-enable SPE\\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input.