四路模拟数字转换器( ADC ) Quad Analog-to-Digital Converter ADC
Product Details
The ADAU1978 incorporates four high performance, analog-to-digital converters ADCs with 2 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta Σ-Δ architecture with continuous time front end for low EMI. An I2C/serial peripheral interface SPI control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1978 uses only a single 3.3 V supply. The part internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The ADAU1978 is available in a 40-lead LFCSP package. The on-chip PLL can derive the master clock from an external clock input or frame clock sample rate clock. When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system.
Note that throughout this data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant.
**APPLICATIONS**
### Features and Benefits
I2S-justified, and TDM modes
型号 | 品牌 | 下载 |
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ADAU1978WBCPZ-RL | ADI 亚德诺 | 下载 |
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ADAU1445YSVZ-3A | ADI 亚德诺 | 下载 |
ADAU1445YSVZ-3A-RL | ADI 亚德诺 | 下载 |
ADAU1446YSTZ-3A-RL | ADI 亚德诺 | 下载 |
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ADAU1451WBCPZ-RL | ADI 亚德诺 | 下载 |
ADAU1450WBCPZ-RL | ADI 亚德诺 | 下载 |