EM639165TS-6G

128-Mbit8M x 16bit，并行接口，工作电压：3.3V

Overview

The EM639165 SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally

configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface all signals are registered on the

positive edge of the clock signal, CLK. Read and write accesses to the SDRAM are burst oriented; accesses

start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

Features

• Fastaccess time from clock:5/5.4 ns

• Fast clock rate: 166/143 MHz

• Fully synchronous operation

• Internal pipelined architecture

• 2M word x 16-bit x 4-bank

• Programmable Mode registers

\- CAS# Latency: 2, or 3

\- Burst Length: 1, 2, 4, 8, or full page

\- Burst Type: interleaved or linear burst

\- Burst stop function

• Auto Refresh and Self Refresh

• 4096 refresh cycles/64ms

• CKE power down mode

• Single +3.3V power supply

• Interface: LVTTL

• 54-pin 400 mil plastic TSOP II package

• Lead-free package is available